Clock Gating Based Energy Efficient ALU Design and Implementation on FPGA

Pandey, B and Yadav, J and Pattanaik, M and Rajoria, N (2013) Clock Gating Based Energy Efficient ALU Design and Implementation on FPGA. In: International Conference on Energy Efficient Technologies for Sustainability, ICEETS 2013, 10-12, April 2013, Nagercoil; India.

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Abstract

In this paper, latch free clock gating techniques is applied in ALU to reduce clock power and dynamic power consumption of ALU. Clock power is 50%, 41.46%, 51.30%, 55.15% and 55.78% of total dynamic power when device operating frequency is 100MHz, 1GHz, 10GHz, 100GHz and 1 THz. After implementation of clock gating techniques in ALU, Clock power reduces to 17.85%, 23.39%, 26.49% and 27.19% of total dynamic power, when device operating frequency is 1GHz, 10GHz, 100GHz and 1 THz. On 1 THz operating frequency, when we use clock gating, there are 72.77% reduction in clock power, 38.88% reduction in IOs power and 44% reduction in dynamic power in compare to power consumption without using clock gating techniques. Target device is 90-nm Spartan-3. There is 14.57% reduction in junction temperature on 10GHz operating frequency in compare to temperature without using clock gating techniques. Clock gating saves power but increases over all area. There is 32.35%, 37.84%, 43.31% and 44% reduction in dynamic current when we use clock gate on 1GHz, 10GHz, 100GHz and 1THz operating frequency respectively

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IITH Creators:
IITH CreatorsORCiD
Item Type: Conference or Workshop Item (Paper)
Uncontrolled Keywords: Clock Gating; Clock Power; Dynamic Current; Dynamic Power; Energy Efficient; Low Power; Operating Frequency
Subjects: Computer science > Big Data Analytics
Divisions: Department of Computer Science & Engineering
Depositing User: Team Library
Date Deposited: 24 Nov 2014 07:25
Last Modified: 24 Nov 2014 07:25
URI: http://raiith.iith.ac.in/id/eprint/924
Publisher URL: http://dx.doi.org/10.1109/ICEETS.2013.6533362
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