A Cost-Aware Framework for Lifetime Reliability of TSV-Based 3D-IC Design

Reddy, Raviteja P. and Acharyya, Amit and Khursheed, Saqib (2020) A Cost-Aware Framework for Lifetime Reliability of TSV-Based 3D-IC Design. IEEE Transactions on Circuits and Systems II: Express Briefs, 67 (11). pp. 2677-2681. ISSN 1549-7747

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The lifetime reliability of 3D-IC is limited due to defects, thermal issues and aging of Through-silicon-via (TSV). The state-of-The-Art methodologies for enhancing reliability are based on the fault tolerance techniques using redundant TSVs. The existing methodlogies do not consider the target lifetime, various failure mechanisms and workload. Thus the performance and cost of 3D-ICs is affected significantly. In this brief, we propose a TSV lifetime reliability aware 3D-IC framework with various TSV failure mechanisms and workload into consideration. Subsequently, validation and evaluation on IWLS'05 benchmark circuits is done for TSV lifetime reliability and compared with existing fault tolerance techniques to provide synergy between TSV count and targeted lifetime reliability of Router and Ring architectures.

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IITH Creators:
IITH CreatorsORCiD
Acharyya, Amithttp://orcid.org/0000-0002-5636-0676
Item Type: Article
Uncontrolled Keywords: 3D IC design; Benchmark circuit; Failure mechanism; Fault tolerance techniques; Lifetime reliability; Ring architecture; State of the art; Through-Silicon-Via (TSV);Electronics packaging; Failure (mechanical); Fault tolerance; Integrated circuit design; Timing circuits
Subjects: Electrical Engineering
Electrical Engineering > Instruments and Instrumentation
Divisions: Department of Electrical Engineering
Depositing User: . LibTrainee 2021
Date Deposited: 22 Jun 2021 04:42
Last Modified: 22 Jun 2021 04:42
URI: http://raiith.iith.ac.in/id/eprint/7974
Publisher URL: http://doi.org/10.1109/TCSII.2020.2970724
OA policy: https://v2.sherpa.ac.uk/id/publication/3424
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