Low-Complexity and High-Speed Architecture Design Methodology for Complex Square Root

Mopuri, Suresh and Acharyya, Amit (2021) Low-Complexity and High-Speed Architecture Design Methodology for Complex Square Root. Circuits, Systems, and Signal Processing. ISSN 0278-081X

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In this paper, we propose a low-complexity and high-speed VLSI architecture design methodology for complex square root computation using COordinate Rotation DIgital Computer (CORDIC). The proposed methodology is independent of angle computation in the CORDIC unlike the state-of-the-art methodologies. The proposed methodology is modelled in VHDL and synthesized under the TSMC 45-nm CMOS technology @ 1 GHz frequency. The synthesis results show that the proposed design saves 18.39%, 4.06% and 17.26%, 2.56% on chip area and power consumption when compared with the state-of-the-art methodologies without loss in accuracy. The proposed design saves the latency of 16 and 14 clock cycles when compared with the state-of-the-art implementations. The proposed design can process 23.4 and 127.344 billion additional samples per one joule energy when compared with the state-of-the-art designs.

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IITH Creators:
IITH CreatorsORCiD
Acharyya, Amithttp://orcid.org/0000-0002-5636-0676
Item Type: Article
Uncontrolled Keywords: Complex square root; CORDIC; VLSI architecture
Subjects: Electrical Engineering
Electrical Engineering > Electrical and Electronic
Divisions: Department of Electrical Engineering
Depositing User: . LibTrainee 2021
Date Deposited: 22 Jun 2021 04:15
Last Modified: 22 Jun 2021 04:15
URI: http://raiith.iith.ac.in/id/eprint/7970
Publisher URL: http://doi.org/10.1007/s00034-021-01738-1
OA policy: https://v2.sherpa.ac.uk/id/publication/15622
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