Optimization of electrical characteristics of Tunnel FET incorporating Gate Engineering

Kothapalli, Susmitha and Pandey, Ullas and Bhowmick, Brinda (2019) Optimization of electrical characteristics of Tunnel FET incorporating Gate Engineering. In: 2nd IEEE International Conference on Modeling of Systems Circuits and Devices, MOS-AK India, 25-27 February 2019, Hyderabad, India.

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In this paper, the electrical characteristics of different structures of TFET including ferrorelectric gate have been studied. The devices have been optimized in order to provide the best values of SS in each device. The best result obtained for SS is 22mV/dec and for I ON /I OFF ratio is 4.4×10 13 . Temperature dependence of each device has been plotted and compared.

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IITH Creators:
IITH CreatorsORCiD
Item Type: Conference or Workshop Item (Paper)
Uncontrolled Keywords: ferroelectric tunnel field effect transistor (Fe-TFET), heterogate, stack gate, Subthreshold swing, temperature dependence, Tunnel field effect transistor (TFET), Indexed in Scopus
Subjects: Electrical Engineering
Divisions: Department of Electrical Engineering
Depositing User: Team Library
Date Deposited: 14 Jan 2020 04:29
Last Modified: 14 Jan 2020 04:29
URI: http://raiith.iith.ac.in/id/eprint/7319
Publisher URL: http://doi.org/10.1109/MOS-AK.2019.8902361
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