A Framework for TSV Based 3D-IC to Analyze Aging and TSV Thermo-Mechanical Stress on Soft Errors

Reddy, Raviteja P and Acharyya, Amit and Khursheed, Saqib (2019) A Framework for TSV Based 3D-IC to Analyze Aging and TSV Thermo-Mechanical Stress on Soft Errors. In: 3rd IEEE International Test Conference in Asia, ITC-Asia, 3-5 September 2019, Tokyo, Japan.

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The CMOS aging, transient effects, and TSV thermomechanical stress degrade the resilience of 3D-ICs. The transients effects lead to soft errors and aggravated with the CMOS Bias temperature instability (BTI). In this paper, we analyze detrimental transient and BTI effect on soft error rate (SER) in 3D-ICs. However, TSV thermomechanical stress presents a considerable benefit by enhancing the critical charge (Qc) and reduce the SER due to decrease in the threshold voltage and increase in mobility of carriers in transistor present out of keep-out-zone and useful range. Therefore we propose a framework to evaluate the effect of transient, BTI, and TSV thermomechanical stress on critical charge and SER in 3D-ICs. Subsequently, through HSPICE simulation we show that for a lifetime of ten years and on the topmost layer of stacked 3D-IC, the reduction in SER of NAND gate by 5.12% - 9.05% and in 6T SRAM 2.51% - 4.76% and 3.77% - 5.64% decrease for storing 0 and 1 respectively.

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IITH Creators:
IITH CreatorsORCiD
Acharyya, Amithttp://orcid.org/0000-0002-5636-0676
Item Type: Conference or Workshop Item (Paper)
Uncontrolled Keywords: 3D-ICAnd SERBTI, Resilience, Through-silicon via (TSV), Indexed in Scopus
Subjects: Electrical Engineering
Divisions: Department of Electrical Engineering
Depositing User: Team Library
Date Deposited: 13 Nov 2019 06:32
Last Modified: 13 Nov 2019 06:32
URI: http://raiith.iith.ac.in/id/eprint/6980
Publisher URL: http://doi.org/10.1109/ITC-Asia.2019.00034
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