Hardware-software co-design of AES on FPGA

Baskaran, S and P, Rajalakshmi (2012) Hardware-software co-design of AES on FPGA. In: International Conference on Advances in Computing, Communications and Informatics, 3-5, August 2012, Chennai; India.

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This paper presents a compact hardware-software co-design of Advanced Encryption Standard (AES) on the field programmable gate arrays (FPGA) designed for low-cost embedded systems. The design uses MicroBlaze, a soft-core processor from Xilinx. The computationally intensive operations of the AES are implemented in hardware for better speed. The sub-byte calculation is designed with the help of the processor carrying out the calculations using hardware blocks implemented using FPGA. By incorporating the processor in the AES design, the total number of slices required to implement the AES algorithm on FPGA is proved to be reduced. The entire AES system design is validated using 460 slices in Spartan-3E XC3S500E, which is one of the low-cost FPGAs

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IITH Creators:
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Item Type: Conference or Workshop Item (Paper)
Uncontrolled Keywords: AES; FPGA
Subjects: Physics > Electricity and electronics
Divisions: Department of Electrical Engineering
Depositing User: Team Library
Date Deposited: 11 Nov 2014 04:11
Last Modified: 24 Aug 2015 07:06
URI: http://raiith.iith.ac.in/id/eprint/676
Publisher URL: http://dx.doi.org/10.1145/2345396.2345575
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