Hardware Implementation of Deep Convolution Neural Network on FPGA

Haribhau, Wankhede Archana and Acharyya, Amit (2019) Hardware Implementation of Deep Convolution Neural Network on FPGA. Masters thesis, Indian institute of technology Hyderabad.

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Deep neural network has gained traction as a state-of-the-art deep learnings approach in a wide range of domains including computer vision, speech recognition, natural language processing, targeted advertising, web search and in biomedical applications. Although DNN offers remarkable accuracy in detection and prediction, it incurs significant power and memory consumption. CPU platform hardly offers computations capacity, and thus graphics processing unit (GPU) have been the centrepiece of many deep learning processes, but increasingly there is a demand for more specialized accelerator for DNN computation. To get a higher throughput along with energy efficient and high-performance accelerator, field programmable gate array (FPGA) and application specific integrated circuit (ASIC) implementation are eye-catching for researchers. But ASICs may not cope with the ever-evolving DNN models. Furthermore, ASICs and customized cores come at the price of high non-recurring engineering cost over long design periods. Hence FPGAs with its better programmable flexibility and parallelism exploitation renders high speed and energy efficiency and proves as an attractive alternative for accelerating DNNs. There have been several studies conducted on the efficient hardware implementation of DCNNs wherein Alex net and VGG Net are explored for computer vision application. Therefore, in this thesis, the main focus is to design a parametrized, efficient and low complex FPGA implementation of other CNN which has not been explored yet including Mini VGG, Compressed VGG and customize the CNN model for image detection and clinical prosthesis respectively. The designed CNNs are synthesized and implemented with Verilog HDL, using Vivado 17.3 simulator. The models are prototyped in Xilinx Virtex V707 and Zynq Ultrascale + (ZCU102) FPGA platform.

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IITH Creators:
IITH CreatorsORCiD
Acharyya, Amithttp://orcid.org/0000-0002-5636-0676
Item Type: Thesis (Masters)
Uncontrolled Keywords: DCNN, CNN, Electromyography (EMG), TD1529
Subjects: Electrical Engineering
Divisions: Department of Electrical Engineering
Depositing User: Team Library
Date Deposited: 08 Aug 2019 05:59
Last Modified: 08 Aug 2019 05:59
URI: http://raiith.iith.ac.in/id/eprint/5888
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