Hardware-Software Codesign based Accelerated and Reconfigurable Methodology for String Matching in Computational Bioinformatics Applications

Gudur, Venkateshwarlu Yellaswamy and Acharyya, Amit (2020) Hardware-Software Codesign based Accelerated and Reconfigurable Methodology for String Matching in Computational Bioinformatics Applications. IEEE/ACM Transactions on Computational Biology and Bioinformatics, 17 (4). pp. 1198-1210. ISSN 1545-5963

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Abstract

Research for new technologies and methods in computational bioinformatics has resulted in many folds biological data generation. To cope up with the ever increasing growth of biological data, there is a need for accelerated solutions in various domains of computational bioinformatics. In these domains, string matching is a most versatile operation performed at various stages of the computational pipeline. For search patterns that are updated with time, there is a need for accelerated and reconfigurable string matching to perform faster searching in the ever-growing biological databases. In this paper, we have proposed an accelerated and real-time reconfigurable methodology for string matching using hardware-software codesign. Using state of the art field programmable gate arrays we have proposed a complete system-on-chip solution for applications that require accelerated as well as real-time reconfigurable string matching. The proposed methodology is the first of its kind novel approach for high-speed string matching that also supports quick reconfiguration by patterns changing with time. It is verified at the string matching stage of protein identification. Experimental results show that the architectures designed using our proposed methodology are 4X faster than state-of-the-art software implementation running on a workstation and 1.5X-4X faster than hardware accelerators available in the literature

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IITH Creators:
IITH CreatorsORCiD
Acharyya, Amithttp://orcid.org/0000-0002-5636-0676
Item Type: Article
Additional Information: In this work, V. Y. Gudur was supported by the Visvesvar-aya PhD Scheme for Electronics & IT by the Ministry of Electronics & Information Technology (MeitY), Government of India. A. Acharyya was supported by the Visve-varaya Young Faculty Fellowship funded by MeitY, Government of India. All the software tools and FPGA boards are supported under the Special Manpower Development Programme for Chips to Systems (SMDP-C2SD) funded by MeitY, Government of India. The authors’ would like to thank the anonymous reviewers for their many insightful comments and suggestions that improved the quality of this paper.
Uncontrolled Keywords: Hardware acceleration; hardware-software codesign; real-time reconfiguration; reconfigurable SoC FPGA; string matching
Subjects: Electrical Engineering
Divisions: Department of Electrical Engineering
Depositing User: Team Library
Date Deposited: 01 Mar 2019 11:03
Last Modified: 07 Nov 2022 08:54
URI: http://raiith.iith.ac.in/id/eprint/4857
Publisher URL: http://doi.org/10.1109/TCBB.2018.2885296
OA policy: https://v2.sherpa.ac.uk/id/publication/10670
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