Das, Santanu and Upadrasta, Ramakrishna
(2018)
Optimizations In Compiler: Vectorization,
Reordering, Register Allocation And Verification
Of Explicitly Parallel Programs.
Masters thesis, Indian Institute of Technology Hyderabad.
Abstract
Compiler Optimizations form a very important part of compiler development as they make a major
difeerence between an average and a great compiler. There are various modules of a compiler-which
opens opportunities for optimizations on various spheres. In this thesis, a comparative study of
vectorization is done exposing the strengths and weaknesses of various contemporary compilers.
Additionally, a study on the impact of vectorization on tiled code is performed. Different strategies
for loop nest optimization is explored. An algorithm for statement reordering in loops to enhance
performance has been developed. An Integer Linear Program formulation is done to improve loop
parallelism, which makes use of loop unrolling and explicitly parallel directives. Finally, an attempt
for optimal loop distribution is made. Following loop nest optimization chapter, an explanation
of interprocedural register allocation(IPRA) for ARM32 and AArch64 is given. Additionally, a
brief description of the problems for implementing IPRA for those architectures is presented. We
conclude the chapter with the performance results with IPRA for those platforms. In the last
chapter, a description of VoPiL, a static OpenMP verifier in LLVM, is presented. A brief description
of the analysis and the results are included.
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