Fast and Cost Effective Computer Aided Design Techniques for 3D Integrated Circuits

Sabbavarapu, S and Acharyya, Amit (2018) Fast and Cost Effective Computer Aided Design Techniques for 3D Integrated Circuits. PhD thesis, Indian Institute of Technology Hyderabad.

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The complexity of design process is increasing proportionally with continuous advancement in the Integrated Circuit (IC). In this current era of System- on- Chip (SoC), the circuit density is raising enormously, driving the designers to come up with a cost-effective solution to accommodate more number of cells in less area without increasing the density and wire-length. The 3D technology is emerging as a promising solution to boost performance with reduced wire-length. Integration of various technologies onto different layers is feasible using 3D integration with support for heterogeneous SoCs. In the 3D IC technology, the system is partitioned into different layers in vertical direction to save the area. The connectivity among the layers established with the connectors/wires popularly known as Through Silicon Vias (TSVs). To materialize the 3DIC design, several methods have been developed, which have several incremental and iterative steps. These steps in conventional digital IC design and automation flow increase the design time and non-recurring engineering cost (NRE), along with area, which are the major driving factors of the IC industry. Reducing all at the same time is a challenge to the research community to come up with a design automation solution. In this work, a novel and unified methodology by merging the frontend and backend stages of the IC design process has been proposed, which eliminates the frontend CAD tool usage to minimize the Design time and NRE cost. It is significantly cost effective interms of NRE costs, Hardware cost (Reduced number of TSVs, Wirelength) and design cost (designer’s effort). Moreover, the complexity of hierarchical design steps is drastically reduced by mapping the input register-transfer level (RTL) description directly to their corresponding physical designs, derived using the existing CAD tools and stored in precomputed technology libraries. The concept of Dynamic Libraries is introduced, which store the layouts of the already designed blocks and their references for the later use in further designs. By using the concept of Dynamic library at higher (block) level of abstraction with the pre-defined physical designs, it resulted in 99.13% - 99.93% of total design time improvement for 2D IC design. Furthermore, the overall physical design cycle in the current era of Integrated Circuit Design Automation is greatly influenced by placement of cells. The existing popular quadratic placement techniques suffer from large placement time due to initial overlaps and large gaps. In order to lower the placement time by avoiding initial overlaps with reduced wire-length, we propose a grouping and merging based placement methodology that is simpler than existing placers and easier to integrate into timing closure flows. As a proof of concept, the proposed methodology is extensively tested on standard benchmark circuits for 2D integration and resulted in reduced placement time by 10% and reduction in wire-length by 13% with zero overlap compared to the state-of-the-art placement techniques. The proposed methodology for 3D integration witnessed the reduction in TSV count, on the benchmark circuits significantly, by 11-12% compared to the stateof- the-art placement tools. It saves the placement time by around 10% due to the overlap free initial placement. Moreover, the proposed methodology reduces the intra layer HPWL remarkably (almost by 13%).

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IITH Creators:
IITH CreatorsORCiD
Acharyya, Amit
Item Type: Thesis (PhD)
Uncontrolled Keywords: EDA, CAD, TSV Cant, Hpower, Area Placement, 3DIC
Subjects: Electrical Engineering
Divisions: Department of Electrical Engineering
Depositing User: Team Library
Date Deposited: 19 Jun 2018 04:37
Last Modified: 21 Sep 2019 07:29
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