Low complexity hardware accelerator for nD FastICA based on coordinate rotation

Bharadwaj, S and Raghuraman, S and Acharyya, Amit (2017) Low complexity hardware accelerator for nD FastICA based on coordinate rotation. In: IEEE International Workshop on Signal Processing Systems, SiPS 2017, October 3-5, 2017, Lorient, France.

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This paper proposes a low complex hardware accelerator algorithmic modification for n-dimensional (nD) FastICA methodology based on Coordinate Rotation Digital Computer (CORDIC) to attain high computation speed. The most complex and time consuming update stage and convergence check required for computation of the nth weight vector are eliminated in the proposed methodology. Using the Gram-Schmidt Orthogonalization stage and normalization stage to calculate nth weight vector in an entirely sequential procedure of CORDIC-based FastICA results in a significant gain in terms of the computation time. The proposed methodology has been functionally verified and validated by applying it for separating 6D speech signals. It has been implemented on hardware using Verilog HDL and synthesized using UMC 180nm technology. The average improvement in computation time obtained by using the proposed methodology for 4D to 6D FastICA with 1024 samples, considering the minimum case of two iterations for nth stage, was found to be 98.79 %. © 2017 IEEE.

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IITH Creators:
IITH CreatorsORCiD
Acharyya, Amithttp://orcid.org/0000-0002-5636-0676
Item Type: Conference or Workshop Item (Paper)
Uncontrolled Keywords: Blind Source Separation, CORDIC, FastICA
Subjects: Electrical Engineering
Divisions: Department of Electrical Engineering
Depositing User: Team Library
Date Deposited: 29 Jan 2018 04:06
Last Modified: 29 Jan 2018 04:06
URI: http://raiith.iith.ac.in/id/eprint/3748
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