Self-compensation scheme for truncation error in fixed width multipliers

Joshi, Pankaj U and Deshmukh, Raghavendra B and Gudur, Venkateshwarlu (2018) Self-compensation scheme for truncation error in fixed width multipliers. IET Circuits, Devices & Systems, 12 (1). pp. 55-62. ISSN 1751-858X

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A novel scheme to design the hardware for error compensation function which self-compensates the truncation error of fixed width multiplier is presented. The proposed method statistically correlates the compensating carries in the truncated part with the carries generated at the truncation boundary in the non-truncated part. The method also utilises the selective dominant carry compensation for controlling the magnitude of error and hardware complexity. The proposed scheme of error compensation in truncated multiplier is investigated for random inputs, Fast Fourier Transform (FFT) application and Finite impulse response (FIR) application. This proposed scheme shows improvement in the major performance parameters such as mean absolute error, mean-square error, maximum error, standard deviation and variance when compared with previously reported schemes. The scheme noticeably decreases the probability of maximum error to 0.22, 0.11 and 0.2 for input scenarios of random, FFT and FIR applications, respectively, which is minimum in comparison to all existing architectures. The scheme is also investigated for the new proposed figure of merit, i.e. energy error product for the truncated multiplier, to select a balanced error and energy optimised truncated multiplier for specific applications.

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IITH Creators:
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Item Type: Article
Uncontrolled Keywords: error compensation, multiplying circuits, statistical analysis, error statistics, self-compensation scheme, truncation error, fixed width multipliers
Subjects: Electrical Engineering
Divisions: Department of Electrical Engineering
Depositing User: Team Library
Date Deposited: 18 Jan 2018 04:41
Last Modified: 18 Jan 2018 04:41
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