Low-Complexity Methodology for Complex Square-Root Computation

Mopuri, Suresh and Acharyya, Amit (2017) Low-Complexity Methodology for Complex Square-Root Computation. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. pp. 1-5. ISSN 1063-8210 (In Press)

Full text not available from this repository. (Request a copy)


In this brief, we propose a low-complexity methodology to compute a complex square root using only a circular coordinate rotation digital computer (CORDIC) as opposed to the state-of-the-art techniques that need both circular as well as hyperbolic CORDICs. Subsequently, an architecture has been designed based on the proposed methodology and implemented on the ASIC platform using the UMC 180-nm Technology node with 1.0 V at 5 MHz. Field programmable gate array (FPGA) prototyping using Xilinx' Virtex-6 (XC6v1x240t) has also been carried out. After thorough theoretical analysis and experimental validations, it can be inferred that the proposed methodology reduces 21.15% slice look up tables (on FPGA platform) and saves 20.25% silicon area overhead and decreases 19% power consumption (on ASIC platform) when compared with the state-of-the-art method without compromising the computational speed, throughput, and accuracy.

[error in script]
IITH Creators:
IITH CreatorsORCiD
Acharyya, Amithttp://orcid.org/0000-0002-5636-0676
Item Type: Article
Uncontrolled Keywords: Computer architecture, Transistors, Hardware, Complexity theory, Very large scale integration, Logic gates, Field programmable gate arrays
Subjects: Electrical Engineering
Divisions: Department of Electrical Engineering
Depositing User: Team Library
Date Deposited: 07 Sep 2017 06:18
Last Modified: 07 Sep 2017 06:18
URI: http://raiith.iith.ac.in/id/eprint/3527
Publisher URL: https://doi.org/10.1109/TVLSI.2017.2740343
OA policy: http://www.sherpa.ac.uk/romeo/issn/1063-8210/
Related URLs:

Actions (login required)

View Item View Item
Statistics for RAIITH ePrint 3527 Statistics for this ePrint Item