A Survey of Techniques for Architecting Processor Components Using Domain-Wall Memory

Mittal, Sparsh (2016) A Survey of Techniques for Architecting Processor Components Using Domain-Wall Memory. ACM Journal on Emerging Technologies in Computing Systems, 13 (2). pp. 1-25. ISSN 1550-4832

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Recent trends of increasing core-count and bandwidth/memory wall have motivated researchers to explore novel memory technologies for designing processor components such as cache, register file, shared memory, and so on. Domain-wall memory (DWM), also known as racetrack memory, is a promising emerging technology due to its non-volatility and very high density. However, use of DWM presents challenges due to characteristics of both DWM itself (e.g., requirement of shift operations, variable latency) and processor components. Recently, several techniques have been proposed to address these challenges. This article presents a survey of architectural techniques for using DWM for designing components in both CPU and GPU. We discuss techniques related to performance, energy, and reliability and also discuss works that compare DWM with other memory technologies. We also highlight the opportunities and obstacles in using DWM for designing processor components. This survey is expected to spark further research in this area and be useful for researchers, chip designers, and computer architects.

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IITH Creators:
IITH CreatorsORCiD
Mittal, Sparshhttp://orcid.org/0000-0002-2908-993X
Item Type: Article
Uncontrolled Keywords: Review; domain-wall memory; shift operations; reliability; performance; energy; cache; CPU; GPU
Subjects: Computer science > Special computer methods
Others > Electronic imaging & Singal processing
Others > Nanotechnology
Divisions: Department of Computer Science & Engineering
Depositing User: Team Library
Date Deposited: 17 Apr 2017 10:26
Last Modified: 17 Oct 2017 09:58
URI: http://raiith.iith.ac.in/id/eprint/3172
Publisher URL: https://doi.org/10.1145/2994550
OA policy: http://www.sherpa.ac.uk/romeo/issn/1550-4832/
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