A Cost-Effective Fault Tolerance Technique for Functional TSV in 3-D ICs

Reddy, R P and Acharyya, Amit and Khursheed, S (2017) A Cost-Effective Fault Tolerance Technique for Functional TSV in 3-D ICs. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, PP (99). ISSN 1063-8210

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Regular and redundant through-silicon via (TSV) interconnects are used in fault tolerance techniques of 3-D IC. However, the fabrication process of TSVs results in defects that reduce the yield and reliability of TSVs. On the other hand, each TSV is associated with a significant amount of on-chip area overhead. Therefore, unlike the state-of-the-art fault tolerance architectures, here we propose the time division multiplexing access (TDMA)-based fault tolerance technique without using any redundant TSVs, which reduces the area overhead and enhances the yield. In the proposed technique, by means of TDMA, we reroute the signal through defect-free TSV. Subsequently, an architecture based on the proposed technique has been designed, evaluated, and validated on logic-on-logic 3-D IWLS'05 benchmark circuits using 130-nm technology node. The proposed technique is found to reduce the area overhead by 28.70%-40.60%, compared to the state-of-the-art architectures and results in a yield of 98.9%-99.8%.

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IITH Creators:
IITH CreatorsORCiD
Acharyya, Amithttp://orcid.org/0000-0002-5636-0676
Item Type: Article
Uncontrolled Keywords: 3-D IC, fault tolerance, through-silicon via (TSV), time division multiplexing access (TDMA), yield
Subjects: Others > Electricity
Divisions: Department of Electrical Engineering
Depositing User: Team Library
Date Deposited: 06 Apr 2017 06:11
Last Modified: 29 Aug 2017 10:48
URI: http://raiith.iith.ac.in/id/eprint/3145
Publisher URL: https://doi.org/10.1109/TVLSI.2017.2681703
OA policy: http://www.sherpa.ac.uk/romeo/issn/1063-8210/
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