Design and Analysis of Soft-Error Resilience Mechanisms for GPU Register File

Mittal, Sparsh and Wang, H and Jog, A and Vetter, J S (2017) Design and Analysis of Soft-Error Resilience Mechanisms for GPU Register File. In: International Conference on VLSI Design (VLSID), Hyderabad, India.

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Modern graphics processing units (GPUs) are using increasingly larger register file (RF) which occupies a large fraction of GPU core area and is very frequently access ed. This makes RF vulnerable to soft-errors (SE). In this paper, we present two techniques for improving SE resilience of GPU RF . First, we propose compressing the RF values for reducing the number of vulnerable bits. We leverage value similarity and the presence of narrow-width values to perform compression at warp or thread-level, respectively. Second, we propose sel ective hardening to design a portion of register entry with SE immun e circuits. By collectively using these techniques, higher r esilience can be provided with lower overhead. Without hardening, our warp and thread-level compression techniques bring 47.0% and 40.8% reduction in SE vulnerability, respectively.

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IITH Creators:
IITH CreatorsORCiD
Mittal, Sparsh
Item Type: Conference or Workshop Item (Paper)
Subjects: Computer science > Big Data Analytics
Divisions: Department of Computer Science & Engineering
Depositing User: Team Library
Date Deposited: 15 Nov 2016 08:23
Last Modified: 17 Oct 2017 10:00
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