A Survey of Techniques for Architecting TLBs

Mittal, Sparsh (2016) A Survey of Techniques for Architecting TLBs. Concurrency and Computation: Practice and Experience. pp. 1-35. ISSN 1532-0626

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“Translation lookaside buffer” (TLB) caches virtual to physical address translation information and is used in systems ranging from embedded devices to high-end servers. Since TLB is accessed very frequently and a TLB miss is extremely costly, prudent management of TLB is important for improving performance and energy efficiency of processors. In this paper, we present a survey of techniques for architecting and managing TLBs. We characterize the techniques across several dimensions to highlight their similarities and distinctions. We believe that this paper will be useful for chip designers, computer architects and system engineers.

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IITH Creators:
IITH CreatorsORCiD
Mittal, Sparshhttp://orcid.org/0000-0002-2908-993X
Item Type: Article
Uncontrolled Keywords: iew; classification; TLB; superpage; prefetching; power management; virtual cache; workload characterization
Subjects: Computer science > Big Data Analytics
Divisions: Department of Computer Science & Engineering
Depositing User: Team Library
Date Deposited: 08 Nov 2016 09:43
Last Modified: 18 Oct 2017 06:51
URI: http://raiith.iith.ac.in/id/eprint/2863
Publisher URL: https://dx.doi.org/10.1002/cpe
OA policy: http://www.sherpa.ac.uk/romeo/issn/1532-0626/
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