0.8 V 450 μW 2.4 GHz PLL using back-gate QVCO for ZigBee/BLE standard in 0.18 μm CMOS

Chary, P P and Peerla, R S and Regulagadda, S S and Naseeb, M A and Acharyya, Amit and P, Rajalakshmi and Mandal, D and Dutta, Asudeb (2016) 0.8 V 450 μW 2.4 GHz PLL using back-gate QVCO for ZigBee/BLE standard in 0.18 μm CMOS. In: International Conference on Microelectronics, Computing and Communications (MICROCOM), JAN 23-25, 2016, Durgapur, India.

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This paper proposes a PLL architecture targeting ZigBee (ZB) and Bluetooth LE (BLE) band. It employs a single well, direct back-gated Quadrature Voltage Controlled Oscillator (QVCO). An efficient, Integer-N, Multi Modulus Divider (MMD) using True Single Phase Clock (TSPC) logic is incorporated in the design to minimize the overall PLL power consumption. The QVCO gives phase noise of-110 dBc/Hz at 1 MHz offset. PLL consumes 450 mu W of power at 0.8 V supply with a settling time less than 25 mu s and core area is 705 mu m x 510 mu m at UMC 0.18 pm CMOS Mixed Mode Technology. PLL is successfully tested with the energy harvesting circuit.

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IITH Creators:
IITH CreatorsORCiD
Acharyya, Amithttp://orcid.org/0000-0002-5636-0676
Item Type: Conference or Workshop Item (Paper)
Uncontrolled Keywords: Single well; PLL; LC-VCO; Back-Gate Coupled; MMD; TSPC; BLE; ZB; Integer-N
Subjects: Computer science > Big Data Analytics
Others > Engineering technology
Divisions: Department of Electrical Engineering
Depositing User: Team Library
Date Deposited: 14 Oct 2016 11:06
Last Modified: 29 Aug 2017 10:58
URI: http://raiith.iith.ac.in/id/eprint/2810
Publisher URL: https://doi.org/10.1109/MicroCom.2016.7522450
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