A 43-nW 10-bit 1-kS/s SAR ADC in 180nm CMOS for biomedical applications

Yadav, K and Patra, P and Dutta, Asudeb (2015) A 43-nW 10-bit 1-kS/s SAR ADC in 180nm CMOS for biomedical applications. In: Asian Pacific Conference on Postgraduate Research In Microelectronics And Electronics (PRIMEASIA), Nov 27-29, 2015, Vasavi Coll Engn, Hyderabad, India.

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This work presents an ultra-low power 10-bit, 1-KS/s successive approximation register (SAR) analog-to-digital converter (ADC) for biomedical applications. To achieve the nano-watt range power consumption, an ultra-low-power design technique has been utilized, inflicting maximum simplicity on the ADC architecture and low transistor count. ADC was designed in 180nm CMOS technology with a 1-V power supply and a 1-kS/s sampling rate for monitoring bio potential signals. The ADC achieves a signal-to-noise plus distortion ratio of 57.16 dB and consumes 43 nW, resulting in a figure of merit of 73 fJ/conversion-step.

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IITH Creators:
IITH CreatorsORCiD
Item Type: Conference or Workshop Item (Paper)
Uncontrolled Keywords: Figure Of Merit (FOM); Signal to Noise plus; Distortion Ratio (SNDR); Successive Approximation Register (SAR)
Subjects: Others > Electricity
Divisions: Department of Electrical Engineering
Depositing User: Team Library
Date Deposited: 22 Aug 2016 05:35
Last Modified: 11 Sep 2017 09:22
URI: http://raiith.iith.ac.in/id/eprint/2667
Publisher URL: https://doi.org/10.1109/PrimeAsia.2015.7450463
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