Energy aware ultra-low power SAR ADC in 180nm CMOS for biomedical application

Yadav, Kunal (2016) Energy aware ultra-low power SAR ADC in 180nm CMOS for biomedical application. Masters thesis, Indian Institute of Technology Hyderabad.


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Power consumption is one of the main design constraints in today’s integrated circuits. For systems powered by batteries, such as implantable biomedical devices, ultra-low power consumption is paramount. In these systems, analog-to-digital converters (ADCs) are key components as the interface between the analog world and the digital domain. This thesis addresses the design challenges, strategies, as well as circuit techniques of ultra-low-power ADCs for medical implant devices. In this thesis four architectures of SAR ADC is implemented with different energy efficiency. In first architecture, conventional SAR ADC was designed in 180nm CMOS technology with a 1-V power supply and a 1-kS/s sampling rate for monitoring bio potential signals, the ADC achieves a signal-to-noise and distortion ratio of 57.16 dB and consumes 43 nW power, resulting in a figure of merit of 73 fJ/conversion-step. In second architecture, Split capacitor SAR ADC was designed in 180nm CMOS with same resolution and sampling speed.

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IITH Creators:
IITH CreatorsORCiD
Item Type: Thesis (Masters)
Uncontrolled Keywords: SAR ADC,CMOS,SINAD,TD633
Subjects: Physics > Electricity and electronics
Divisions: Department of Electrical Engineering
Depositing User: Library Staff
Date Deposited: 25 Jul 2016 06:47
Last Modified: 30 Jul 2019 09:17
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