A 0.5 V, 0.13 nW, 4-Transistor Over Temperature Protection Circuit for SoCs

Bhattacharjee, Indranil and Amara, Mohith and Chowdary, Gajendranath (2022) A 0.5 V, 0.13 nW, 4-Transistor Over Temperature Protection Circuit for SoCs. In: 2022 IEEE International Symposium on Circuits and Systems, ISCAS 2022, 27 May-1 June 2022, Austin.

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A 0.13 nW ultra-low-power over-temperature-protection circuit is proposed for highly integrated System-on-Chips (SoC). The circuit detects a temperature of 120{circ} text{C} but can be programmed for other temperature thresholds. The temperature detection is achieved by comparing a reference voltage with a 2-transistor ultra-low-power inverter architecture. The 2transistor inverter is designed to have a proportional-to-absolute-temperature (PTAT) threshold characteristic, and the reference voltage is generated on-chip with a 2-transistor reference. The design is implemented in 0.18 mu text{m} CMOS technology and occupies an area of 0.0117 text{mm}{2}. The design operates from 0.5 V supply voltage and has a line sensitivity of 0.1{circ} text{C}/text{V} and a hysteresis width of 7.7{circ} text{C}, as seen from simulations. The trim-free design has a worst-case process variation of 4%. © 2022 IEEE.

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IITH Creators:
IITH CreatorsORCiD
Chowdary, GajendranathUNSPECIFIED
Item Type: Conference or Workshop Item (Paper)
Additional Information: ACKNOWLEDGMENT The authors would like to thank the Science and Engineering Research Board, DST, GoI, for funding this work under grant ECR/2018/002836.
Uncontrolled Keywords: hysteresis; over-temperature-protection; PTAT; subthreshold reference; ultra-low-power; voltage reference
Subjects: Electrical Engineering
Divisions: Department of Electrical Engineering
Depositing User: Ms Palak Jain
Date Deposited: 22 May 2023 09:29
Last Modified: 22 May 2023 09:29
URI: http://raiith.iith.ac.in/id/eprint/11474
Publisher URL: https://doi.org/10.1109/ISCAS48785.2022.9937546
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