High‐speed, high‐resolution methodology for portable universal radar target‐echo simulator

Daggula, Rajender and Vasudeva, Bevara and Kamal, Manisha and Acharyya, Amit (2022) High‐speed, high‐resolution methodology for portable universal radar target‐echo simulator. Microwave and Optical Technology Letters. ISSN 0895-2477

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Abstract

In this paper, digital parallelization and fractional delay-based novel methods are proposed for the realization of high bandwidth, high-resolution Ku-band radar target simulator with 2.5 GHz intermediate frequency. High bandwidth waveform from radar is sampled by high-speed Analog to Digital Converter, and samples are parallelized in Field Programmable Gate Array (FPGA) to work at the nominal clock frequency. In Digital RF Memory-based target simulator, for finer range resolution, the FPGA clock frequency needs to be increased, which leads to increased system design complexity. The finer range resolution is accomplished without altering the system clock frequency using variable fractional delay filters and the digital parallelization methodology is proposed in this paper. The maximum target range that can be simulated is 20 km. As a result, memory requirements, computational complexity, and power dissipation are reduced. Finally, simulation and implementation results are presented. © 2022 Wiley Periodicals LLC.

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IITH Creators:
IITH CreatorsORCiD
Acharyya, Amithttp://orcid.org/0000-0002-5636-0676
Item Type: Article
Uncontrolled Keywords: DRFM; FPGA; radar cross section; radar target simulators
Subjects: Electrical Engineering
Divisions: Department of Electrical Engineering
Depositing User: Ms Palak Jain
Date Deposited: 22 May 2023 09:46
Last Modified: 22 May 2023 09:46
URI: http://raiith.iith.ac.in/id/eprint/11448
Publisher URL: https://doi.org/10.1002/mop.33520
OA policy: https://v2.sherpa.ac.uk/id/publication/15194
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