Study of gate current in advanced MOS architectures

Gauhar, Ghulam Ali and Chenchety, Abhishek and Yenugula, Hashish and Georgiev, Vihar and Asenov, Asen and Badami, Oves (2022) Study of gate current in advanced MOS architectures. Solid-State Electronics, 194. pp. 1-4. ISSN 0038-1101

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Abstract

We have carried out a comprehensive study of the gate current (I-G) in advanced MOS architectures for different gate lengths and cross-section areas using an in-house simulation tool. We have considered only direct tunneling under the assumption that trap concentration and therefore the trap assisted current would be small in a matured technology. We have also studied the impact of the interfacial (IL) SiO2 layer on the gate current in the high-kappa gate stack. Our results suggest that IL leads to an increase in the gate current for equivalent EOT. They also highlight that reduction in the cross-section area leads to a significant increase in the I-G.

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IITH Creators:
IITH CreatorsORCiD
Badami, OvesUNSPECIFIED
Item Type: Article
Uncontrolled Keywords: Gate currentTunnelingWKB Approximation
Subjects: Electrical Engineering
Divisions: Department of Electrical Engineering
Depositing User: . LibTrainee 2021
Date Deposited: 31 Oct 2022 10:26
Last Modified: 31 Oct 2022 10:26
URI: http://raiith.iith.ac.in/id/eprint/11111
Publisher URL: http://doi.org/10.1016/j.sse.2022.108345
OA policy: https://v2.sherpa.ac.uk/id/publication/4706
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