An FPGA Based Energy-Efficient Read Mapper With Parallel Filtering and In-Situ Verification

Gudur, Venkateshwarlu Yellaswamy and Maheshwari, Sidharth and Acharyya, Amit and et al, . (2022) An FPGA Based Energy-Efficient Read Mapper With Parallel Filtering and In-Situ Verification. IEEE/ACM Transactions on Computational Biology and Bioinformatics, 19 (5). pp. 2697-2711. ISSN 1545-5963

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Abstract

In the assembly pipeline of Whole Genome Sequencing (WGS), read mapping is a widely used method to re-assemble the genome. It employs approximate string matching and dynamic programming-based algorithms on a large volume of data and associated structures, making it a computationally intensive process. Currently, the state-of-the-art data centers for genome sequencing incur substantial setup and energy costs for maintaining hardware, data storage and cooling systems. To enable low-cost genomics, we propose an energy-efficient architectural methodology for read mapping using a single system-on-chip (SoC) platform. The proposed methodology is based on the q-gram lemma and designed using a novel architecture for filtering and verification. The filtering algorithm is designed using a parallel sorted q-gram lemma based method for the first time, and it is complemented by an in-situ verification routine using parallel Myers bit-vector algorithm. We have implemented our design on the Zynq Ultrascale+ XCZU9EG MPSoC platform. It is then extensively validated using real genomic data to demonstrate up to 7.8x energy reduction and up to 13.3x less resource utilization when compared with the state-of-the-art software and hardware approaches.

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IITH Creators:
IITH CreatorsORCiD
Acharyya, Amithttp://orcid.org/0000-0002-5636-0676
Item Type: Article
Additional Information: V. Y. Gudur's research is supported by the Visvesvaraya PhD Scheme for Electronics & IT by MeitY, Government of India (GOI) and partly by the IOT Based Holistic Prevention and Prediction of CVD (i-PREACT) project under ICPS Programme, Department of Science & Technology, GOI. S. Maheshwari's research is supported by EPSRC DTP scholarship at Newcastle University, U.K. The authors would like to acknowledge the funding supports from the Royal Society Exchange (IE161183) and EPSRC IAA `Whipserable' projects.
Uncontrolled Keywords: Bioinformatics , Genomics , Filtering , Field programmable gate arrays , Hardware , Sequential analysis , Software
Subjects: Electrical Engineering
Divisions: Department of Electrical Engineering
Depositing User: . LibTrainee 2021
Date Deposited: 25 Oct 2022 08:09
Last Modified: 25 Oct 2022 08:09
URI: http://raiith.iith.ac.in/id/eprint/11034
Publisher URL: http://doi.org/10.1109/TCBB.2021.3106311
OA policy: https://v2.sherpa.ac.uk/id/publication/10670
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