VLSI Architecture Design Methodology for Deep learning based Upper Limb and Lower Limb Movement Classification for Rehabilitation Application

Nimbekar, Anagha and Dinesh, Y V Sai and Gautam, Arvind and Hunsigida, Vidhumouli and Nali, Appa Rao and Acharyya, Amit (2022) VLSI Architecture Design Methodology for Deep learning based Upper Limb and Lower Limb Movement Classification for Rehabilitation Application. In: 13th IEEE Latin American Symposium on Circuits and Systems, LASCAS 2022, 1 March 2022 through 4 March 2022, Santiago.

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Abstract

Recently, many works have proposed an highly accurate deep learning based movement classification algorithms for the assistive technology applications. But very less importance is given for it's corresponding hardward implementation. In this paper we proposed an VLSI architecture design methodology for deep learning based movement classification for assistive technology applications. LoCoMo-Net and MyoNet are the two Deep learning based networks proposed by Gautam et al [1] [2] for upper limb and lower limb for assistive technology. The proposed architecture is capable enough to adapt both the networks. We have implemented the architecture on ZYNQ ultra-textscale + textMPSoC textzcu102 textFPGA. LoCoMo-Net consumes 3.5 Watts of on chip power and MyoNet consumes 5 Watts of on chip power on the FPGA. LoCoMo-Net takes 1.876ms of time to classify the task and MyoNet takes 61.988ms of time to classify the task on FPGA. © 2022 IEEE.

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IITH Creators:
IITH CreatorsORCiD
Acharyya, Amithttp://orcid.org/0000-0002-5636-0676
Item Type: Conference or Workshop Item (Paper)
Additional Information: This work is partially supported by Ministry of Electronics and Information Technology (Govt of India) funded “Indigenous Intelligent and Scalable Neuromorphic Multi Chip for AI Training and Inference Solutions” project dated March 2021.
Uncontrolled Keywords: Convolutional Neural Network (CNN); LoCoMO-Net; Long Short Term Memory (LSTM); movement classification; MyoNet; sEMG
Subjects: Electrical Engineering
Divisions: Department of Electrical Engineering
Depositing User: . LibTrainee 2021
Date Deposited: 18 Oct 2022 09:59
Last Modified: 18 Oct 2022 09:59
URI: http://raiith.iith.ac.in/id/eprint/11006
Publisher URL: http://doi.org/10.1109/LASCAS53948.2022.9789091
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