Area efficient in-plane nanomagnetic multiplier and convolution architecture design

Sivasubramani, Santhosh and Debroy, Sanghamitra and Acharyya, Amit (2021) Area efficient in-plane nanomagnetic multiplier and convolution architecture design. Nano Express, 2 (2). pp. 1-10. ISSN 2632-959X

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In this study, we propose a nanomagnetic logic (NML) based 2 bit multiplier architecture design for the first time to the best of author's knowledge. This complex combinational logic (nanomagnetic multiplier) design proposed is built by exploiting shape, positional hybrid anisotropy and the ferromagnetically coupled fixed input majority gate. Subsequently, we extend this proposed multiplier architecture along with the NML adder architecture in introducing NML based convolution architecture design which is efficient in terms of number of nanomagnets, majority gates and clock-cycles. The proposed NML design yields 1/421%-72%, 1/426%-42%, 1/436%-63%, and 1/420%-68%, reduction in the required number of nanomagnets, majority gate, clock cycles and energy compared to the state-of-the-art designs. © 2021 The Author(s). Published by IOP Publishing Ltd.

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IITH Creators:
IITH CreatorsORCiD
Acharyya, Amit
Item Type: Article
Additional Information: The authors would like to thank Indian Nano electronics Users Program, IIT Bombay (IITB) for providing the facilities for fabrication and electrical characterization of the device at Centre of Excellence in Nanoelectronics (CEN), IITB. Computational support on clusters at AESICD Laboratory IIT Hyderabad is gratefully acknowledged. SS acknowledges the Institute Post-Doctoral Fellowship by IIT Hyderabad. The authors declare no competing financial and non-financial interests. Indigenous Intelligent and Scalable Neuromorphic Multichip for AI Training and Inference Solutions" project funded by the Ministry of electronics and Information technology (MEITY), Government of India with Approval No. 4(7)/2021-ITEA dated 8th March 2021 is acknowledged.
Uncontrolled Keywords: architecture design methodology; area efficient nanomagnetic convolution; dipole coupling; ferromagnetically coupled majority gate; in plane magnetization; nanomagnetic Logic; nanomagnetic multiplier
Subjects: Electrical Engineering
Divisions: Department of Electrical Engineering
Depositing User: . LibTrainee 2021
Date Deposited: 05 Aug 2022 05:39
Last Modified: 05 Aug 2022 05:39
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