Mitigating Read Disturbance Errors in STT-RAM Caches by Using Data Compression

Mittal, Sparsh (2019) Mitigating Read Disturbance Errors in STT-RAM Caches by Using Data Compression. In: Nanoelectronics. Elsevier, pp. 133-152. ISBN 978-0-12-813353-8

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Abstract

Due to its high density and close to SRAM read latency, spin transfer torque RAM (STT-RAM) is considered one of the most promising emerging memory technologies for designing large last level caches (LLCs). However, in a deep submicron region, STT-RAM shows read disturbance error (RDE) whereby a read operation may modify the stored data value, and this presents a severe threat to performance and reliability of STT-RAM caches. In this paper, we present a technique, named SHIELD, to mitigate RDE in STT-RAM LLCs. SHIELD uses data compression to reduce the number of read operations from STT-RAM blocks to avoid RDE, and also to reduce the number of bits written to cache during both write and restore operations. Experimental results have shown that SHIELD provides significant improvement in performance and energy efficiency. SHIELD consumes smaller energy than the two previous RDE-mitigation techniques, namely high current restore required read (HCRR, also called restore-after-read) and low current long latency read (LCLL) and even an ideal RDE-free STT-RAM cache.

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IITH Creators:
IITH CreatorsORCiD
Mittal, Sparshhttp://orcid.org/0000-0002-2908-993X
Item Type: Book Section
Subjects: Computer science
Divisions: Department of Computer Science & Engineering
Depositing User: Team Library
Date Deposited: 01 Jan 2020 09:24
Last Modified: 01 Jan 2020 09:24
URI: http://raiith.iith.ac.in/id/eprint/7291
Publisher URL: http://doi.org/10.1016/B978-0-12-813353-8.00001-4
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