Improved Electro-Thermal Performance in FinFETs using SOD Technology for 7nm node High Performance Logic Devices

Venkateswarlu, Sankatali and Sudarsanan, Akhil and Nayak, Kaushik (2019) Improved Electro-Thermal Performance in FinFETs using SOD Technology for 7nm node High Performance Logic Devices. In: International Conference on Solid State Devices and Materials, 2 - 5 September 2019, Nagoya University, Japan.

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Abstract

Self-heating effect (SHE) is a serious issue in ultradown scaled 3-D transistors especially in silicon-on-insulator (SOI) transistors due to lower thermal conductivity SiO2 buried oxide (BOX) region. However, recently, diamond has become an attractive dielectric material due to its superior thermal conductivity (kth = 2000 W.m-1 .K-1 ). In this paper, we designed FinFETs with diamond as BOX region material (i.e. SOD FinFET) and investigated the SHE in comparison with bulk and SOI FinFETs with similar design parameters using 3D TCAD analysis from 14nm to 7nm CMOS technology node. The SOD FinFET shows better heat removal from device active (channel) region by lowering the active region temperature by 17% and 28% compared Bulk and SOI designs respectively. The effective thermal resistance (Rth,eff) is also lowered by 40% and 54% compared Bulk and SOI FinFETs respectively. This result in lower degradation in drive current for SOD FinFET with efficient active region heat energy removal enabling continued energy-efficient scaling to sub-7nm node. The impact of thermal boundary conditions (Rth,GSD and TA) on transistor performance are also investigated in this work.

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IITH Creators:
IITH CreatorsORCiD
Nayak, KaushikUNSPECIFIED
Item Type: Conference or Workshop Item (Paper)
Subjects: Electrical Engineering
Divisions: Department of Electrical Engineering
Depositing User: Team Library
Date Deposited: 24 Dec 2019 09:20
Last Modified: 24 Dec 2019 09:20
URI: http://raiith.iith.ac.in/id/eprint/7246
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