Spur Reduction in Phase Lock Loop Using Charge Pump Current Matching Technique

M D, Jamal (2012) Spur Reduction in Phase Lock Loop Using Charge Pump Current Matching Technique. Masters thesis, Indian Institute of Technology Hyderabad.

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Abstract

A clock with high spectral purity is required in many applications. The spectral purity of the clock source is critical for the overall system performance. Phase locked-loops (PLLs) are commonly used to generate well-timed on-chip clocks in high performance. The most important application of the phase locked loops (PLL) is for clock generation and clock recovery in microprocessor, networking, communication systems, ADCs to accurately define sampling moments and frequency synthesizers. The concept of PLL technique was first described in 1932. Since the invention of PLL, design of PLL has remained challenging because of requirements such as fast operation, low power consumption, less noisy electronic equipment's. Phase Frequency Detector (PFD), Charge pump and Voltage Controlled Oscillator (VCO) are the non-ideality components of PLL.

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IITH Creators:
IITH CreatorsORCiD
Item Type: Thesis (Masters)
Uncontrolled Keywords: TD43
Subjects: Others > Electricity
Divisions: Department of Electrical Engineering
Depositing User: Team Library
Date Deposited: 11 Nov 2014 05:38
Last Modified: 16 Nov 2015 06:50
URI: http://raiith.iith.ac.in/id/eprint/697
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