Cut-less Technology Mapping Using Shannon Factor Graph with on-the-fly Size Reduction

Basireddy, Karunakar R and Sabbavarapu, Srinivas and Acharyya, Amit and et al, . (2018) Cut-less Technology Mapping Using Shannon Factor Graph with on-the-fly Size Reduction. Journal of Low Power Electronics, 14 (3). pp. 448-457. ISSN 1546-1998

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Abstract

The cut-based technology mapping algorithms are computationally expensive as they require cutenumeration, pruning, and computation of local function of cuts and their canonical form. The number of cuts to be enumerated increases exponentially (O(n K )) with the cut size (k) and graph size (n), due to which the design time and storage for storing the cuts become a bottleneck. Therefore, as a solution, we present a new graph data structure, called Shannon Factor Graph (SFG) to facilitate the cut-less technology mapping, thereby eliminating the need of cut-enumeration and its subsequent steps. Besides, we propose an on-the-fly graph size reduction algorithm to minimize the size of the subject graph, which in turn improves the circuit area (gate count) of the target graph. When compared with the cut-based technology mapping approaches using standard benchmarks, proposed methodology reduces the design time by up to 32× and storage requirements by 282×. Subsequently, comparison with Synopsys DC shows that proposed approach has only an average area overhead of 2.6%.

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IITH Creators:
IITH CreatorsORCiD
Acharyya, Amithttp://orcid.org/0000-0002-5636-0676
Item Type: Article
Uncontrolled Keywords: CAD FOR VLSI, CUT ENUMERATION, LOGIC SYNTHESIS, TECHNOLOGY MAPPING, Indexed in Scopus
Subjects: Electrical Engineering
Divisions: Department of Electrical Engineering
Depositing User: Library Staff
Date Deposited: 14 Nov 2019 05:11
Last Modified: 14 Nov 2019 05:11
URI: http://raiith.iith.ac.in/id/eprint/6850
Publisher URL: https://doi.org/10.1166/jolpe.2018.1573
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