A survey of techniques for improving error-resilience of DRAM

Mittal, Sparsh and Inukonda, Maruthi S (2018) A survey of techniques for improving error-resilience of DRAM. Journal of Systems Architecture, 91. pp. 11-40. ISSN 1383-7621

Full text not available from this repository. (Request a copy)

Abstract

Aggressive process scaling and increasing demands of performance/cost efficiency have exacerbated the incidences and impact of errors in DRAM systems. Due to this, improvements in DRAM reliability has received significant attention in recent years from both academia and industry. In this paper, we present a survey of techniques for improving reliability of DRAM-based main memory. We classify the works based on key parameters to emphasize their similarities and differences. This paper is expected to be useful for computer architects, chip-designers and researchers in the area of memory/system-reliability.

[error in script]
IITH Creators:
IITH CreatorsORCiD
Mittal, Sparshhttp://orcid.org/0000-0002-2908-993X
Item Type: Article
Uncontrolled Keywords: DRAM, Reliability, Memory, Error correcting code (ECC), Chipkill, Stacked DRAM, In-DRAM ECC, Data compression
Subjects: Computer science
Divisions: Department of Computer Science & Engineering
Depositing User: Team Library
Date Deposited: 08 Jan 2019 06:51
Last Modified: 08 Jan 2019 06:51
URI: http://raiith.iith.ac.in/id/eprint/4674
Publisher URL: http://doi.org/10.1016/j.sysarc.2018.09.004
OA policy: http://www.sherpa.ac.uk/romeo/issn/1383-7621/
Related URLs:

Actions (login required)

View Item View Item
Statistics for RAIITH ePrint 4674 Statistics for this ePrint Item