DESTINY: A Comprehensive Tool with 3D and Multi-Level Cell Memory Modeling Capability

Mittal, Sparsh and Wang, Rujia and Vetter, Jeffrey (2017) DESTINY: A Comprehensive Tool with 3D and Multi-Level Cell Memory Modeling Capability. Journal of Low Power Electronics and Applications, 7 (3). p. 23. ISSN 2079-9268

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Abstract

To enable the design of large capacity memory structures, novel memory technologies such as non-volatile memory (NVM) and novel fabrication approaches, e.g., 3D stacking and multi-level cell (MLC) design have been explored. The existing modeling tools, however, cover only a few memory technologies, technology nodes and fabrication approaches. We present DESTINY, a tool for modeling 2D/3D memories designed using SRAM, resistive RAM (ReRAM), spin transfer torque RAM (STT-RAM), phase change RAM (PCM) and embedded DRAM (eDRAM) and 2D memories designed using spin orbit torque RAM (SOT-RAM), domain wall memory (DWM) and Flash memory. In addition to single-level cell (SLC) designs for all of these memories, DESTINY also supports modeling MLC designs for NVMs. We have extensively validated DESTINY against commercial and research prototypes of these memories. DESTINY is very useful for performing design-space exploration across several dimensions, such as optimizing for a target (e.g., latency, area or energy-delay product) for a given memory technology, choosing the suitable memory technology or fabrication method (i.e., 2D v/s 3D) for a given optimization target, etc. We believe that DESTINY will boost studies of next-generation memory architectures used in systems ranging from mobile devices to extreme-scale supercomputers. The latest source-code of DESTINY is available from the following git repository: https://bitbucket.org/sparsh_mittal/destiny_v2.

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IITH Creators:
IITH CreatorsORCiD
Mittal, Sparshhttp://orcid.org/0000-0002-2908-993X
Item Type: Article
Uncontrolled Keywords: Cache, DRAM, DWM, eDRAM, Emerging memory technologies, Flash, Modeling tool, Non-volatile memory (NVM or NVRAM), Open-source, PCM, ReRAM, SOT-RAM, SRAM, STT-RAM
Subjects: Computer science
Divisions: Department of Computer Science & Engineering
Depositing User: Team Library
Date Deposited: 08 Nov 2017 04:08
Last Modified: 08 Nov 2017 04:08
URI: http://raiith.iith.ac.in/id/eprint/3663
Publisher URL: http://doi.org/10.3390/jlpea7030023
OA policy: http://www.sherpa.ac.uk/romeo/issn/2079-9268/
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