Improved Wire Length-Driven Placement Technique for Minimizing Wire Length, Area and Timing

Sabbavarapu, Srinivas and Basireddy, Karunakar R and Acharyya, Amit and Khursheed, Saqib (2017) Improved Wire Length-Driven Placement Technique for Minimizing Wire Length, Area and Timing. Journal of Low Power Electronics, 13 (3). pp. 456-471. ISSN 1546-1998

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Abstract

The placement of cells in Integrated Circuit Design Automation has a major influence on overall design cycle. The existing popular quadratic placement techniques suffer from overlaps, large placement effort and time. In order to lower the placement overhead and to avoid the overlaps with reduced wire length, we propose a grouping and merging based placement methodology that is simpler than existing placers and easier to integrate into timing-closure flows. As a proof of concept, the proposed methodology is extensively tested on standard benchmark circuits. The proposed methodology resulted in 5× placement time reduction, 13% reduction in wire-length and 11% reduction in area with zero overlap.

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IITH Creators:
IITH CreatorsORCiD
Acharyya, Amithttp://orcid.org/0000-0002-5636-0676
Item Type: Article
Uncontrolled Keywords: GROUPING; HALF PERIMETER WIRE-LENGTH (HPWL); MACRO; MERGING; OVERLAP; PLACEMENT EFFORT
Subjects: Electrical Engineering > Electrical and Electronic
Divisions: Department of Electrical Engineering
Depositing User: Team Library
Date Deposited: 26 Sep 2017 04:15
Last Modified: 19 Jun 2018 04:45
URI: http://raiith.iith.ac.in/id/eprint/3583
Publisher URL: https://doi.org/10.1166/jolpe.2017.1506
OA policy: http://www.sherpa.ac.uk/romeo/issn/1546-1998/
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