XStat: Statistical X-filling algorithm for peak capture power reduction in scan tests

A S, Trinadh and Potluri, S and Balachandran, S and Ch, Sobhan Babu and Kamakoti, V (2014) XStat: Statistical X-filling algorithm for peak capture power reduction in scan tests. Journal of Low Power Electronics, 10 (1). pp. 107-115. ISSN 1546-1998

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Excessive power dissipation can cause high voltage droop on the power grid, leading to timing failures. Since test power dissipation is typically higher than functional power, test peak power minimization becomes very important in order to avoid test induced timing failures. Test cubes for large designs are usually dominated by don't care bits, making X-leveraging algorithms promising for test power reduction. In this paper, we show that X-bit statistics can be used to reorder test vectors on scan based architectures realized using toggle-masking flip flops. Based on this, the paper also presents an algorithm namely balanced X-filling that when applied to ITC'99 circuits, reduced the peak capture power by 7.4% on the average and 40.3% in the best case. Additionally XStat improved the running time for Test Vector Ordering and X-filling phases compared to the best known techniques.

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IITH Creators:
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Item Type: Article
Uncontrolled Keywords: Design for Testability (DFT); Peak Capture-Power; Scan-Based Testing; Test Vector Ordering (TVO); X-Bit Statistics
Subjects: Physics > Electricity and electronics
Divisions: Department of Electrical Engineering
Depositing User: Team Library
Date Deposited: 30 Dec 2014 07:37
Last Modified: 14 Aug 2017 10:15
URI: http://raiith.iith.ac.in/id/eprint/1280
Publisher URL: https://doi.org/10.1166/jolpe.2014.1302
OA policy: http://www.sherpa.ac.uk/romeo/issn/1546-1998/
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