A reconfigurable high speed architecture design for discrete hilbert transform

Reddy, P S and Mopuri, S and Acharyya, Amit (2014) A reconfigurable high speed architecture design for discrete hilbert transform. IEEE Signal Processing Letters, 21 (11). pp. 1413-1417. ISSN 1070-9908

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Abstract

This letter proposes a high-speed and reconfigurable Discrete Hilbert Transform architecture design methodology targeting the real-time applications including Cyber-Physical systems, Internet of Things or Remote Health-Monitoring where the same chip-set needs to be used for various purposes under real-time scenario. By using this architecture we are able to get Discrete Hilbert Transform for any given M-point by re-using N-point Discrete Hilbert Transform as a kernel. Here N and M are multiple of 4 and N respectively. Subsequently we provide the architecture design details and compare the proposed architecture with the conventional state-of-the-art architecture. Thorough theoretical analysis and experimental comparison results show that the proposed design is twice as fast and reconfigurability is also achieved simultaneously

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IITH Creators:
IITH CreatorsORCiD
Acharyya, Amithttp://orcid.org/0000-0002-5636-0676
Item Type: Article
Uncontrolled Keywords: Engineering controlled terms: Design; Embedded systems
Subjects: Physics > Electricity and electronics
Divisions: Department of Electrical Engineering
Depositing User: Team Library
Date Deposited: 16 Dec 2014 11:37
Last Modified: 29 Aug 2017 10:55
URI: http://raiith.iith.ac.in/id/eprint/1156
Publisher URL: https://doi.org/10.1109/LSP.2014.2333745
OA policy: http://www.sherpa.ac.uk/romeo/issn/1070-9908/
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